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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 document no. m15406ej7v0ds00 (7th edition) date published march 2002 ns cp (k) printed in japan mos integrated circuit pd4632312-x 32m-bit cmos mobile specified ram 2m-word by 16-bit extended temperature operation data sheet the mark shows major revised points. description the pd4632312-x is a high speed, low power, 33,554,432 bits (2,097,152 words by 16 bits) cmos mobile specified ram featuring low power static ram compatible function and pin configuration. the pd4632312-x is fabricated with advanced cmos technology using one-transistor memory cell. the pd4632312-x is packed in 77-pin tape fbga. features ? 2,097,152 words by 16 bits organization ? fast access time: 85, 95, 105 ns (max.) ? fast page access time: 35, 40, 45 ns (max.) ? byte data control: /lb (i/o0 - i/o7), /ub (i/o8 - i/o15) ? low voltage operation (b version: v cc = 2.6 to 3.1 v, c version: v cc = 2.3 to 2.7 v, be version: v cc = 2.6 to 3.1 v (chip), v cc q = 1.65 to 1.95 v (i/o), ce version: v cc = 2.3 to 2.7 v (chip), v cc q = 1.65 to 1.95 v (i/o)) ? operating ambient temperature: t a = ?25 to +85 c ? output enable input for easy application ? chip enable input: /cs pin ? standby mode input: mode pin ? standby mode1: normal standby (memory cell data hold valid) ? standby mode2: density of memory cell data hold is variable product name access operating operating supply current time supply voltage ambient at operating at standby a (max.) ns (max.) v temperature ma (max.) density of data hold chip i/o c 32m bits 16m bits 8m bits 4m bits 0m bit pd4632312-bxxx 80 note 2.7 to 3.1 ? ?25 to +85 35 100 70 60 50 10 85 2.6 to 3.1 pd4632312-cxxx 95 2.3 to 2.7 pd4632312-bexxx 95 2.6 to 3.1 1.65 to 1.95 pd4632312-cexxx 105 2.3 to 2.7 note under development
data sheet m15406ej7v0ds 2 pd4632312-x ordering information part number package access time operating operating remark ns (max.) supply voltage temperature vc chip i/o pd4632312f9-b85x-bt3 77-pin tape fbga (12 x 7) 85 2.6 to 3.1 ? ?25 to +85 b version pd4632312f9-c95x-bt3 95 2.3 to 2.7 c version pd4632312f9-be95x-bt3 95 2.6 to 3.1 1.65 to 1.95 be version pd4632312f9-ce10x-bt3 105 2.3 to 2.7 ce version
data sheet m15406ej7v0ds 3 pd4632312-x pin configuration /xxx indicates active low si gnal. 77-pin tape fbga (12 x 7) [ pd4632312f9-bxxx-bt3] [ pd4632312f9-cxxx-bt3] [ pd4632312f9-bexxx-bt3] [ pd4632312f9-cexxx-bt3] top view gnd i/o9 i/o5 a7 /oe i/o7 i/o4 i/o0 a6 a18 a11 a8 a5 i/o8 i/o12 a13 a17 nc nc i/o10 nc /we v cc a16 i/o11 nc nc a12 i/o6 i/o13 a9 a15 a19 i/o14 /cs i/o15 i/o1 a1 a2 a4 a10 v cc q i/o2 a0 a3 mode a20 a14 /lb nc nc /ub i/o3 nc nc gnd top view bottom view 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 pnmlkjhgfedcba abcdefghjklmnp abcdefghjklmnp nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc notes 1. b, c version : nc 2. some signals can be applied because this pin is not internally connected. remark refer to package drawing for the index mark. a0 - a20 : address inputs i/o0 - i/o15 : data inputs / outputs /cs : chip select mode : standby mode /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply v cc q note1 : input / output power supply gnd : ground nc note2 : no connection
data sheet m15406ej7v0ds 4 pd4632312-x block diagram address buffer memory cell array 33,554,432 bits input data controller a0 a20 i/o8 - i/o15 sense amplifier / switching circuit column decoder /we /oe /ub /lb output data controller i/o0 - i/o7 v cc v cc q gnd /cs mode address buffer refresh counter row decoder refresh control standby mode control note note be, ce versions only.
data sheet m15406ej7v0ds 5 pd4632312-x truth table /cs mode /oe /we /lb /ub mode i/o supply i/o0 - i/o7 i/o8 - i/o15 current hh not selected (standby mode 1) high impedance high impedance i sb1 hl not selected (standby mode 2) note1 high impedance high impedance i sb2 lhhh output disable high impedance high impedance i cca l h l l word read d out d out l h lower byte read d out high impedance h l upper byte read high impedance d out h h output disable high impedance high impedance lll word write d in d in l h lower byte write d in high impedance h l upper byte write high impedance d in h h write-abort note2 high impedance high impedance caution mode pin must be fixed to high except standby mode 2. notes 1. during normal operation, make /cs = v ih , mode = v il , the device enters the standby mode 2. however, make /cs = v ih or v il , and mode = v il at power application, the device enters the standby mode 2. 2. write data can not be written to the memory cell. remark : v ih or v il , h: v ih , l: v il ,
data sheet m15406ej7v0ds 6 pd4632312-x contents 1. initialization ............................................................................................................. .....................................................7 2. partial refresh ............................................................................................................. .................................................8 2.1 standby mode............................................................................................................... ...........................................8 2.2 density switching.......................................................................................................... ...........................................8 2.3 standby mode status transition............................................................................................. .................................8 2.4 addresses for which partial refresh is supported .......................................................................... ......................9 3. page read operation ........................................................................................................ ........................................10 3.1 features of page read operation ........................................................................................... .............................10 3.2 page length ............................................................................................................... ..........................................10 3.3 page-corresponding addresses............................................................................................... .............................10 3.4 page start address........................................................................................................ .......................................10 3.5 page direction ............................................................................................................ ..........................................10 3.6 interrupt during page read operation...................................................................................... ............................10 3.7 eight-word start page read operation prohibition .......................................................................... ...................10 3.8 cautions for eight-word page read operation............................................................................... .....................11 4. mode register settings...................................................................................................... .........................................12 4.1 mode register setting method .............................................................................................. ...............................12 4.2 cautions for setting mode register ........................................................................................ ..............................13 5. electrical specifications .................................................................................................. ...........................................14 6. timing charts.............................................................................................................. ...............................................21 7. package drawing ............................................................................................................ ...........................................42 8. recommended soldering conditions ........................................................................................... .............................43 9. revision history ........................................................................................................... ..............................................44
data sheet m15406ej7v0ds 7 pd4632312-x 1. initialization the pd4632312-x is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, before turning on the power, a 200 s or longer wait time must precede any signal toggling. (2) after the wait time, read operation must be performed at least 3 times. after that, it can be normal operation. figure1-1. initialization timing chart v cc , v cc q v cc (min.) v cc q (min.) v ih (min.) v ih (min.) t rc t cp 200 s address (input) /cs (input) mode (input) wait time power on read operation 3 times normal operation cautions 1. following power application, make mode and /cs high level during the wait time interval. 2. following power application, make mode high level during the wait time and three read operations. 3. the read operation must satisfy the specs described on page 17 (read cycle). 4. the address is don?t care (v ih or v il ) during read operation. 5. read operation must be executed with toggled the /cs pin. 6. to prevent bus contention, it is recommended to set /oe to high level. 7. do not input data to the i/o pins if /oe is low level during a read operation.
data sheet m15406ej7v0ds 8 pd4632312-x 2. partial refresh 2.1 standby mode in addition to the regular standby mode (standby mode 1) with a 32m bits density, standby mode 2, which performs partial refresh, is also provided. 2.2 density switching in standby mode 2, the densities that can be selected for performing refresh are 16m bits, 8m bits, 4m bits, and 0m bit. the density for performing refresh can be set with the mode register. (for how to perform mode register settings, refer to section 4. mode register settings .) 2.3 standby mode status transition in standby mode 1, both /cs and mode are high level, and in standby mode 2, /cs is high level and mode is low level. in standby mode 2, if 0m bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from standby mode 2. when the density has been set to 16m bits, 8m bits, or 4m bits in standby mode 2, it is not necessary to perform initialization to return to normal operation from standby mode 2. for the timing charts, refer to figure 6-26. standby mode timing chart , figure 6-27. standby mode 2 (data invalid) entry / recovery timing chart .
data sheet m15406ej7v0ds 9 pd4632312-x figure 2-1. standby mode state machine power on /cs = v ih , mode = v ih active mode = v ih /cs = v ih , mode = v ih /cs = v ih , mode = v il /cs = v ih , mode = v il /cs = v il , mode = v ih standby mode 1 /cs = v il initial state wait time 200 s dummy read 3 times standby mode 2 (data invalid) /cs = v il , mode = v ih /cs = v ih , mode = v il standby mode 2 (16m bits / 8m bits / 4m bits) /cs = v ih , mode = v il 2.4 addresses for which partial refresh is supported data hold density correspondence address 16m bits 000000h to 0fffffh 8m bits 000000h to 07ffffh 4m bits 000000h to 03ffffh
data sheet m15406ej7v0ds 10 pd4632312-x 3. page read operation 3.1 features of page read operation features 4 word mode 8 word mode page length 4 words 8 words page read-corresponding addresses a1, a0 a2, a1, a0 page read start address don?t care (a2, a1, a0) = (v il , v il , v il ) page direction don?t care sequential increment interrupt during page read operation enabled note prohibited note an interrupt is output when /cs = h or in case a2 or a higher address changes. 3.2 page length four words and eight words are supported as the page lengths. the page length is set with the mode register. once the page length is set in the mode register, this setting is retained until it is set again. (for how to perform mode register settings, refer to section 4. mode register settings .) 3.3 page-corresponding addresses the four-word page read-enabled addresses are a1 and a0. fix addresses other than a1 and a0 during four -word page read. the eight-word page read-enabled addresses are a2, a1, and a0. fix addresses other than a2, a1, and a0 during 8-word page read operation. 3.4 page start address since random page read is supported for four-word pages, any address can be used as the page start address. random page read is not supported for eight-word pages. since the page read start addresses are only (a2, a1, a0) = (v il , v il , v il ), it is not possible to start page read from any address other than (a2, a1, a0) = (v il , v il , v il ). 3.5 page direction since random page read is possible for four-word pages, there is not restriction on the page direction. random page read is not supported for eight-word pages. the page direction in this case is sequential increment. 3.6 interrupt during page read operation when generating an interrupt during four-word page read, either make /cs high level or change a2 and higher addresses. generating an interrupt during eight-word read is prohibited. 3.7 eight-word start page read operation prohibition when an eight-word page read has been started, starting a page read with write-modify-read is prohibited. to start page read, do so from normal read. also, when an eight-word page read has been started, the /oe pin cannot be toggled. for the timing chart, refer to figure 6-9. 8 words page read start after write modify read cycle timing chart , figure 6-11. 8 words 2 continuous read cycles timing chart.
data sheet m15406ej7v0ds 11 pd4632312-x 3.8 cautions for eight-word page read operation to perform normal read (a20 to a3: fixed) from normal read of (a2, a1, a0) = (v il , v il , v il ) to (a2, a1, a0) = (v il , v il , v ih ) with the eight-word page set with the mode register, be sure to toggle /oe for normal read (a2, a1, a0) = (v il , v il , v il ). at this time, observe the /oe to address setup time (t oas ) and /oe pulse width (t op ) standard value. when /oe is fixed to low level with normal read (a20 to a3: fixed) from normal read of (a2, a1, a0) = (v il , v il , v il ) to (a2, a1, a0) = (v il , v il , v ih ), eight-word page read starts. also, when performing a read operation to (a2, a1, a0) = (v il , v il , v ih ) (a20 to a3 are fixed) from when (a2, a1, a0) = (v il , v il , v il ) are in a write-abort state (/we = l, however, write data cannot be written to the memory cell because /lb, /um = h), an 8-word page read operation is started. for the timing chart, refer to figure 6-6. 8 words page read cycle timing chart , figure 6-12. 8 words normal read cycle timing chart and figure 6-13 8 words write-abort to read cycle timing chart .
data sheet m15406ej7v0ds 12 pd4632312-x 4. mode register settings the page length and partial refresh density can be set using the mode register. since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. when not using page read, set the mode register to random-accessible 4-word page read mode. when not using partial refresh, set the mode register to any value. partial refresh mode will not be entered unless /cs = h, mode = l, regardless of the register setting. once the page length and partial refresh density have been set in the mode register, these settings are retained until they are set again, while applying the power supply. however, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. 4.1 mode register setting method the mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address (1fffffh). the mode register setting is a continuous four-cycle operation (two read cycles and two write cycles). commands are written to the command register. the command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. for the timing chart and flow chart, refer to figure 6-24. mode register setting timing chart , figure 6-25. mode register setting flow chart . table 4-1. shows the commands and command sequences.
data sheet m15406ej7v0ds 13 pd4632312-x table 4-1. command sequence command sequence 1st bus cycle (read cycle) 2nd bus cycle (read cycle) 3rd bus cycle (write cycle) 4th bus cycle (write cycle) partial refresh density page length address data address data address data address data 16m bits 4 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 00h 8 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 04h 8m bits 4 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 01h 8 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 05h 4m bits 4 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 02h 8 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 06h 0m bit 4 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 03h 8 words 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 07h 4th bus cycle (write cycle) i/o 1514131211109876543210 mode register setting 0000000000000pl pd page length 0 4 words 18 words i/o1 i/o0 density partial refresh 0 0 16m bits density 0 1 8m bits 1 0 4m bits 1 1 0m bit 4.2 cautions for setting mode register since, for the mode register setting, the internal counter status is judged by toggling /cs and /oe, toggle /cs at every cycle during entry (read cycle twice, write cycle twice), and toggle /oe like /cs at the first and second read cycles. if incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register are not performed correctly. when the highest address (1fffffh) is read consecutively three or more times, the mode register setting entries are cancelled. once the page length and partial refresh density have been set in the mode register, these settings are retained until they are set again. for the timing chart and flow chart, refer to figure 6-24. mode register setting timing chart , figure 6-25. mode register setting flow chart .
data sheet m15406ej7v0ds 14 pd4632312-x 5. electrical specifications absolute maximum ratings parameter symbol condition rating unit pd4632312-bxxx, pd4632312-bexxx, pd4632312-cxxx pd4632312-cexxx supply voltage v cc ?0.5 note to +4.0 ?0.5 note to +4.0 v input / output supply voltage v cc q ? ?0.5 note to +4.0 v input / output voltage v t ?0.5 note to v cc + 0.4 (4.0 v max.) ?0.5 note to v cc q + 0.4 (4.0 v max.) v operating ambient temperature t a ?25 to +85 ?25 to +85 c storage temperature t stg ?55 to +125 ?55 to +125 c note ?1.0 v (min.) (pulse width: 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition pd4632312 -bxxx pd4632312 -cxxx pd4632312 -bexxx pd4632312 -cexxx unit min. max. min. max. min. max. min. max. supply voltage v cc 2.6 3.1 2.3 2.7 2.6 3.1 2.3 2.7 v input / output supply voltage v cc q ? ? ? ? 1.65 1.95 1.65 1.95 v high level input voltage v ih 0.8v cc v cc +0.3 0.8v cc v cc +0.3 0.8v cc qv cc q+0.3 0.8v cc qv cc q+0.3 v low level input voltage v il ?0.3 note 0.2v cc ?0.3 note 0.2v cc ?0.3 note 0.2v cc q ?0.3 note 0.2v cc qv operating ambient temperature t a ?25 +85 ?25 +85 ?25 +85 ?25 +85 c note ?0.5 v (min.) (pulse width: 30 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are not 100% tested.
data sheet m15406ej7v0ds 15 pd4632312-x dc characteristics (recommended operating conditions unless otherwise noted) (1/2) parameter symbol test condition density of pd4632312-bxxx, unit data hold pd4632312-cxxx min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cs = v il , minimum cycle time, 35 ma i i/o = 0 ma standby supply current i sb1 /cs v cc ? 0.2 v, mode v cc ? 0.2 v 32m bits 100 a i sb2 /cs v cc ? 0.2 v, mode 0.2 v 16m bits 70 8m bits 60 4m bits 50 0m bit 10 high level output voltage v oh i oh = ?0.5 ma 0.8v cc v low level output voltage v ol i ol = 1 ma 0.2v cc v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of product classifications. dc characteristics (recommended operating conditions unless otherwise noted) (2/2) parameter symbol test condition density of pd4632312-bexxx, unit data hold pd4632312-cexxx min. typ. max. input leakage current i li v in = 0 v to v cc q ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc q, /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cs = v il , minimum cycle time, 35 ma i i/o = 0 ma standby supply current i sb1 /cs v cc ? 0.2 v, mode v cc ? 0.2 v 32m bits 100 a i sb2 /cs v cc ? 0.2 v, mode 0.2 v 16m bits 70 8m bits 60 4m bits 50 0m bit 10 high level output voltage v oh i oh = ?0.5 ma 0.8v cc qv low level output voltage v ol i ol = 1 ma 0.2v cc qv remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of product classifications.
data sheet m15406ej7v0ds 16 pd4632312-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions [ pd4632312-b85x, pd4632312-c95x ] input waveform (rise and fall time 5 ns) test points 0.2vcc 0.8vcc vcc / 2 vcc / 2 vcc gnd 5ns output waveform test points vcc / 2 vcc / 2 [ pd4632312-be95x, pd4632312-ce10x ] input waveform (rise and fall time 5 ns) test points 0.2vccq 0.8vccq vccq / 2 vccq / 2 vccq gnd 5ns output waveform test points vccq / 2 vccq / 2 output load ac characteristics directed with the note should be measured with the output load shown in figure 5-1, figure 5-2 . figure 5-1. (b, c version) c l : 30 pf 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow ) i/o (output) 50 ? z o = 50 ? c l v cc / 2 i/o (output) 50 ? z o = 50 ? c l v cc q / 2 figure 5-2. (be, ce version) c l : 30 pf 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow )
data sheet m15406ej7v0ds 17 pd4632312-x read cycle parameter symbol pd4632312 pd4632312 pd4632312 pd4632312 unit note -b85x -c95x -be95x -ce10x min. max. min. max. min. max. min. max. read cycle time t rc 85 10,000 95 10,000 95 10,000 105 10,000 ns 1 identical address read cycle time t rc1 85 10,000 95 10,000 95 10,000 105 10,000 ns 2 address skew time t skew 15 15 15 15 ns 3 /cs pulse width t cp 10 10 10 10 ns address access time t aa 85 95 95 105 ns 4 /cs access time t acs 85 95 95 105 ns /oe to output valid t oe 35 45 45 50 ns 5 /lb, /ub to output valid t ba 35 45 45 50 ns output hold from address change t oh 10 10 10 10 ns /cs to output in low impedance t clz 10 10 10 10 ns /oe to output in low impedance t olz 5555ns /lb, /ub to output in low impedance t blz 5555ns /cs to output in high impedance t chz 25 25 25 25 ns /oe to output in high impedance t ohz 25 25 25 25 ns /lb, /ub to output in high impedance t bhz 25 25 25 25 ns notes 1. one read cycle (t rc ) must satisfy the minimum value (t rc(min.) ) and maximum value (t rc(max.) = 10 s). t rc indicates the time from the /cs low level input point or address change start point, whichever is later, to the /cs high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t rc . 1) time from address change start point to /cs high level input point (address access) 2) time from address change start point to next address change start point (address access) 3) time from /cs low level input point to next address change start point (/cs access) 4) time from /cs low level input point to /cs high level input point (/cs access) 2. the identical address read cycle time (t rc1 ) is the cycle time of one read operation when performing continuous read operations toggling /oe , /lb, and /ub with the address fixed and /cs low level. perform settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cs from high level to low level, t skew is the time from the /cs low level input point until the next address is determined. 2) when switching /cs from low level to high level, t skew is the time from the address change start point to the /cs high level input point. 3) when /cs is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cs is active, t skew is not subject to limitations when /cs is switched from high level to low level following address determination, or when the address is changed after /cs is switched from low level to high level. 4. regarding t aa and t acs , only t aa is satisfied during address access (refer to 1) and 2) of note 1 ), and only t acs is satisfied during /cs access (refer to 3) of note 1 ). 5. regarding t ba and t oe , only t ba is satisfied if /oe becomes active later than /ub and /lb, and only t oe is satisfied if /ub and /lb become active before /oe.
data sheet m15406ej7v0ds 18 pd4632312-x page read cycle parameter symbol pd4632312 pd4632312 pd4632312 pd4632312 unit note -b85x -c95x -be95x -ce10x min. max. min. max. min. max. min. max. page read cycle time t prc 40 45 40 45 ns page access time t paa 35 40 40 45 ns normal to page read cycle time t nprc 10,000 10,000 10,000 10,000 ns 1 /oe to address setup time t oas ?5 ?5 ?5 ?5 ns 2 /oe pulse width t op 10 10 10 10 ns notes 1. normal to page read cycle time (t nprc ) is the total cycle time for one 4 word page read and one 8 word page read. perform settings to that (t nprc ) is 10 s or less. 2. /oe to address setup time (t oas ) and /oe pulse width (t op ) are effective only when 8 word page read is set. (refer to section 3.8. cautions for eight-word page read operation .) standby mode entry / exit parameter symbol min. max. unit note /cs high to mode low t cm 0ns mode high to /cs low t mc 30 ns cautions 1. make mode and /cs high level during the wait time interval. 2. make mode high level during the wait time and three read operations. 3. the read operation must satisfy the specs described on page 17 (read cycle). 4. the address is don?t care (v ih or v il ) during read operation. 5. read operation must be executed with toggled the /cs pin. 6. to prevent bus contention, it is recommended to set /oe to high level. 7. do not input data to the i/o pins if /oe is low level during a read operation.
data sheet m15406ej7v0ds 19 pd4632312-x write cycle parameter symbol pd4632312 pd4632312 pd4632312 pd4632312 unit note -b85x -c95x -be95x -ce10x min. max. min. max. min. max. min. max. write cycle time t wc 85 10,000 95 10,000 95 10,000 105 10,000 ns 1 identical address write cycle time t wc1 85 10,000 95 10,000 95 10,000 105 10,000 ns 2 address skew time t skew 15 15 15 15 ns 3 /cs to end of write t cw 40 50 50 55 ns 4 /lb, /ub to end of write t bw 30 35 35 40 ns address valid to end of write t aw 35 40 40 45 ns write pulse width t wp 30 35 35 40 ns write recovery time t wr 20 20 20 20 ns 5 /cs pulse width t cp 10 10 10 10 ns address setup time t as 0000ns byte write hold time t bwh 20 20 20 20 ns data valid to end of write t dw 20 30 30 40 ns data hold time t dh 0000ns /oe to output in low impedance t olz 5555ns /we to output in high impedance t whz 25 25 25 25 ns /oe to output in high impedance t ohz 25 25 25 25 ns output active from end of write t ow 5555ns notes 1. one write cycle (t wc ) must satisfy the minimum value (t wc(min.) ) and the maximum value (t wc(max.) = 10 s). t wc indicates the time from the /cs low level input point or address change start point, whichever is after, to the /cs high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t wc . 1) time from address change start point to /cs high level input point 2) time from address change start point to next address change start point 3) time from /cs low level input point to next address change start point 4) time from /cs low level input point to /cs high level input point 2. the identical address read cycle time (t wc1 ) is the cycle time of one write cycle when performing continuous write operations with the address fixed and /cs low level, changing /lb and /ub at the same time, and toggling /we, as well as when performing a continuous write toggling /lb and /ub. make settings so that the sum (t wc ) of the identical address write cycle times (t wc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cs from high level to low level, t skew is the time from the /cs low level input point until the next address is determined. 2) when switching /cs from low level to high level, t skew is the time from the address change start point to the /cs high level input point. 3) when /cs is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cs is active, t skew is not subject to limitations when /cs is switched from high level to low level following address determination, or when the address is changed after /cs is switched from low level to high level.
data sheet m15406ej7v0ds 20 pd4632312-x 4. definition of write start and write end /cs /we /lb, /ub status write start pattern 1 h to l l l if /we, /lb, /ub are low level, time when /cs changes from high level to low level write start pattern 2 l h to l l if /cs, /lb, /ub are low level, time when /we changes from high level to low level write start pattern 3 l l h to l if /cs, /we are low level, time when /lb or /ub changes from high level to low level write end pattern 1 l l to h l if /cs, /we, /lb, /ub are low level, time when /we changes from low level to high level write end pattern 2 l l l to h when /cs, /we, /lb, /ub are low level, time when /lb or /ub changes from low level to high level 5. definition of write end recovery time (t wr ) 1) time from write end to address change start point, or from write end to /cs high level input point 2) when /cs, /lb, /ub are low level and continuously written to the identical address, time from /we high level input point to /we low level input point 3) when /cs, /we are low level and continuously written to the identical address, time from /lb or /ub high level input point, whichever is later, to /lb or /ub low level input point, whichever is earlier. 4) when /cs is low level and continuously written to the identical address, time from write end to point at which /we , /lb, or /ub starts to change from high level to low level, whichever is earliest. read write cycle parameter symbol min. max. unit note read write cycle time t rwc 10,000 ns 1, 2 byte write setup time t bws 20 ns byte read setup time t brs 20 ns notes 1. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. 2. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a read is performed at the identical address using /ub following a write using /lb with /cs low level, or when a read is performed using /lb following a write using /ub.
data sheet m15406ej7v0ds 21 pd4632312-x 6. timing charts figure 6-1. read cycle timing chart 1 t chz t oh t clz t acs /cs (input) i/o (output) t blz t ba t bhz /oe (input) /lb, /ub (input) t oe t skew t skew t cp t cp t rc t olz t ohz t chz t clz t acs i/o (output) t blz t ba t bhz /oe (input) /lb, /ub (input) t oe t skew t cp t cp t rc t olz t ohz /cs (input) t skew high impedance high impedance address (input) address (input) data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high.
data sheet m15406ej7v0ds 22 pd4632312-x t acs /cs (input) address (input) i/o (output) /oe (input) t skew t skew t skew /lb, /ub (input) data out data out data out data out data out high impedance t rc t rc t aa t oe t olz t blz t oh t cp t rc t chz t acs t clz t bhz t ba t blz t skew t cp t rc t chz t acs t clz t bhz t ba t blz t bhz t chz t oh t aa t ohz t rc t clz t ba t oh caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. figure 6-2. read cycle timing chart 2
data sheet m15406ej7v0ds 23 pd4632312-x t acs /cs (input) address (input) i/o8~15 (output) /oe (input) t skew /lb (input) t clz t skew t skew t skew t skew t rc t rc t rc t rc t rc i/o0~7 (output) /ub (input) data out data out data out data out hi-z high impedance t blz t blz t olz t oe t ba t ba t oh t bhz t bhz t ohz t oh t oh t bhz t ohz t oh t bhz t ohz t aa t blz t olz t oe t ba t blz t olz t oe t ba t aa caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value f or the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. figure 6-3. read cycle timing chart 3
data sheet m15406ej7v0ds 24 pd4632312-x figure 6-4. read cycle timing chart 4 /cs (input) address (input) /lb, /ub (input) data out i/o (output) t skew t skew high impedance high impedance t rc1 t ba t ba t rc1 t rc /oe (input) t acs t oe t oe data out t olz t blz t olz t blz t ohz t bhz t ohz t bhz note note caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. note to perform a continuous read toggling /oe, /ub, and /lb with /cs low level at an identical address, make settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. remark in read cycle, /we should be fixed to high.
data sheet m15406ej7v0ds 25 pd4632312-x figure 6-5. 4 words page read cycle timing chart i/o (output) /cs (input) /oe, /lb, /ub (input) t nprc t skew t prc t prc t prc t rc t paa t oh t paa t oh t paa t oh t oh t acs q n t oe t ba t skew t chz t ohz t bhz a n a n+1 a n+2 a n+3 q n+1 q n+2 q n+3 address (a2 - a20) (input) page address (a0, a1) (input) figure 6-6. 8 words page read cycle timing chart i/o (output) /cs (input) /oe, /lb, /ub (input) t nprc t skew t prc t prc t prc t rc t paa t oh t paa t oh t paa t oh t acs t qe t skew t oh t ba a n+1 a n+2 a n+3 a n+7 q n q n+1 q n+2 q n+3 q n+7 t chz t ohz t bhz a n t paa t oh t prc t paa t oh t prc t paa t oh t prc t paa t oh q n+4 q n+5 q n+6 a n+4 a n+5 a n+6 t prc address (a3 - a20) (input) page address (a0 - a2) (input)
data sheet m15406ej7v0ds 26 pd4632312-x /cs (input) /oe(input) address (input) /cs (input) /oe (input) address (input) 4 word page read continuous operation a m+1 a m+2 a m+3 a m+7 a m a m+4 a m+5 a m+6 a n a n +1 a n+2 a n+3 a n+7 a n+4 a n+5 a n+6 a m+1 a m+2 a m+3 a m a n a n +1 a n+2 a n+3 a p a p+1 a p+2 a p+3 t nprc t prc t rc t prc t prc t prc t prc t prc t prc t prc t prc t rc t rc t nprc t nprc t nprc t prc t rc t prc t prc t prc t prc t prc t prc t rc t prc t prc t prc t prc t prc t prc t prc t nprc 8 word page read continuous operation t paa t oh t paa t oh t paa t oh t oh t aa, t acs, t oe q m t ohz q m+1 q m+2 q m+3 t clz t paa t oh t paa t oh t paa t oh t oh t olz q n t oe t ohz q n+1 q n+2 q n+3 t paa t oh t paa t oh t paa t oh t oh t olz q p t oe t chz q p+1 q p+2 q p+3 t paa t oh t paa t oh t paa t oh t aa , t acs , t oe t oh q m q m+1 q m+2 q m+3 q m+7 t ohz t paa t oh t paa t oh t paa t oh t paa t oh q m+4 q m+5 q m+6 t paa t oh t paa t oh t paa t oh t oe t oh q n q n+1 q n+2 q n+3 q n+7 t chz t paa t oh t paa t oh t paa t oh t paa t oh q n+4 q n+5 q n+6 t olz high impedance high impedance high impedance t ohz t ohz t clz t olz t olz i/o ( output ) i/o (output) high impedance high impedance high impedance figure 6-7. 4 / 8 words continuous page read cycle timing chart
data sheet m15406ej7v0ds 27 pd4632312-x figure 6-8. prohibition of 8 words page read start after write modify read cycle timing chart a n+1 a n+2 a n+3 a n+7 a n a n+4 a n+5 a n+6 t as t wp t wr t prc t rc t prc t prc t prc t prc t prc t prc t wc t nprc /cs (input) /oe (input) address (input) /we(input) caution 8 words page read cannot be started with write modify read. 8 words page read can be started by unselecting /cs after writing to a n and then reading a n again. figure 6-9. 8 words page read start after write modify read timing chart a n+1 a n+2 a n+3 a n+7 a n a n+4 a n+5 a n+6 t as t wp t wr t prc t rc t prc t prc t prc t prc t prc t prc t wc t nprc t cp /cs (input) /oe (input) address (input) /we (input) i/o (input/output) t paa t oh t paa t oh t paa t oh t acs t oe t oh q n q n+1 q n+2 q n+3 q n+7 t chz t ohz t paa t oh t paa t oh t paa t oh t paa t oh q n+4 q n+5 q n+6 t dw t dh data in high impedance
data sheet m15406ej7v0ds 28 pd4632312-x figure 6-10. prohibition of 8 words 2 continuous read cycles timing chart a n+1 a n+2 a n+3 a n+7 a n a n+4 a n+5 a n+6 t prc t rc t prc t prc t prc t prc t prc t prc t rc t nprc /cs (input) /oe (input) address (input) figure 6-11. 8 words 2 continuous read cycles timing chart a n+1 a n+2 a n+3 a n+7 a n a n+4 a n+5 a n+6 t prc t rc t prc t prc t prc t prc t prc t prc t wc t nprc t cp /cs (input) /oe (input) address (input) i/o (output) t paa t oh t paa t oh t paa t oh t acs t oe t oh q n q n+1 q n+2 q n+3 q n+7 t chz t ohz t paa t oh t paa t oh t paa t oh t paa t oh q n+4 q n+5 q n+6 high impedance t olz t chz t aa t olz t acs t oe q n high impedance t ohz t clz
data sheet m15406ej7v0ds 29 pd4632312-x figure 6-12. 8 words normal read cycle timing chart t blz /oe (input) /cs (input) address (input) i/o (output) /lb,/ub (input) t skew t acs t skew t skew t aa t oe t oe t ba t ba t oas t rc t rc t blz t clz t olz t olz t ohz t bhz t bhz (a2, a1, a0) = (v il , v il , v il ) (a2, a1, a0) = (v il , v il , v ih ) t ohz note note data out data out t op caution always toggle /oe. if /oe is fixed to low level, page read starts. note a3 and higher address do not change. (a20 to a3) addresses are constant. figure 6-13. 8 words write-abort to read cycle timing chart t blz /oe (input) /cs (input) address (input) i/o (output) /lb, /ub (input) t skew t wp t skew t skew t aa t oe t ba t wr t wc t rc t dw t olz t bhz (a2, a1, a0) = (v il , v il , v il ) (a2, a1, a0) = (v il , v il , v ih ) t ohz note note data in data out /we (input) t as t dh t chz caution when performing a read operation to (a2, a1, a0) = (v il , v il , v ih ) from when (a2, a1, a0) = (v il , v il , v il ) are in a write-abort state, it is recognized as a page read. note a3 and higher address do not change. (a20 toa3) addresses are constant.
data sheet m15406ej7v0ds 30 pd4632312-x figure 6-14. write cycle timing chart 1 t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp t wr /we (input) t skew t cp high impedance data in t wc t cw t skew t dw t dh data in t as t wp t wr t as t bw t wc t cw t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp t wr /we (input) t skew t cp high impedance data in t wc t skew t dw t dh data in t wp t wr t bw t wc t cw t cw t skew cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 31 pd4632312-x figure 6-15. write cycle timing chart 2 (/we controlled) t cw t aw /cs (input) address (input) t as t wp /we (input) t skew t skew t aw t dw t dh i/o (input/output) t wr t ow t aw t skew t cp t whz high impedance high impedance high impedance high impedance high impedance /oe (input) t ohz t olz t wp t as t as t wc t wc t wc t wp t wr t wr data in indefinite t dw t dh t dw t dh t skew data in data in /cs (input) address (input) /we (input) t dw t dh i/o (input) t skew t skew high impedance high impedance high impedance t wc1 data in t as t wp t wp t wr t dw t dh data in t wc1 /lb, /ub (input) t bw t skew t wc t wr note note data out cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cs low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remarks 1. write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub. 2. when /we is at low, the i/o pins are always high impedance. when /we is at high, read operation is executed. therefore /oe should be at high to make the i/o pins high impedance.
data sheet m15406ej7v0ds 32 pd4632312-x figure 6-16. write cycle timing chart 3 (/cs controlled) t as t cw i/o (input) t wr t wc /we (input) /cs (input) address (input) /lb, /ub (input) t dw t dh high impedance high impedance high impedance t wc data in data in t dw t dh t cw t wr t as t as t cw i/o (input) t wr t wc /we (input) /cs (input) address (input) /lb, /ub (input) t dw t dh high impedance high impedance high impedance t wc data in data in t dw t dh t cw t wr t as cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 33 pd4632312-x figure 6-17. write cycle timing chart 4 (/lb, /ub controlled 1) t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp /we (input) t skew high impedance data in t wc t cw t skew t dw t dh data in t wr t as t bw t as t wc t aw t wr t bw t dw t dh high impedance address (input) /lb, /ub (input) i/o (input) /cs (input) t wp t wr /we (input) t skew high impedance data in t wc t cw t skew t dw t dh data in t as t wc t bw t as t wr t aw cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 34 pd4632312-x figure 6-18. write cycle timing chart 5 (/lb, /ub controlled 2) /cs (input) address (input) /lb, /ub (input) t dw t dh i/o (input) t skew t skew high impedance high impedance high impedance t wc1 data in t as t bw t bw t wr t dw t dh data in t wc1 t wr t wc /we (input) t wp note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cs low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 35 pd4632312-x figure 6-19. write cycle timing chart 6 (/lb, /ub independent controlled 1) t wp t as t cw i/o0~7 (input) t wr t wc1 /we (input) /cs (input) address (input) /lb (input) t bw high impedance high impedance /ub (input) t bw t wc1 data in t dw t dh t wr i/o8~15 (input) high impedance high impedance t dw t dh data in t wc note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cs low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 36 pd4632312-x figure 6-20. write cycle timing chart 7 (/lb, /ub independent controlled 2) t wp t as t cw i/o0~7 (input) t wc /we (input) /cs (input) address (input) /lb (input) t bw high impedance high impedance /ub (input) t bw data in t dw t dh i/o8~15 (input) high impedance high impedance t dw t dh data in t wr t wr t as t bwh t cw t wp cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 37 pd4632312-x figure 6-21. read write cycle timing chart 1 (/lb, /ub independent controlled 1) t wp i/o0~7 (output) t bws t rc1 /we (input) /cs (input) address (input) /lb (input) high impedance high impedance /ub (input) t bw t wc1 data out t wr i/o8~15 (input) high impedance high impedance t dw t dh data in t rwc t clz t blz t bhz t acs t aa note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 38 pd4632312-x figure 6-22. read write cycle timing chart 2 (/lb, /ub independent controlled 2) t wp i/o0~7 (input) t rc1 /we (input) /cs (input) address (input) /lb (input) high impedance high impedance /ub (input) t bw t wc1 data out t wr i/o8~15 (output) high impedance high impedance t dw t dh data in t rwc t blz t bhz t brs t ba t cw t as note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 39 pd4632312-x figure 6-23. read write cycle timing chart 3 (/lb, /ub independent controlled 3) t wp i/o0~7 (input) t rc1 /we (input) /cs (input) address (input) /lb (input) high impedance high impedance /ub (input) t bw t wc1 data out t wr i/o8~15 (output) high impedance high impedance t dw t dh data in t rwc t blz t bhz t ba t cw t as note note cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cs low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cs, /we, /lb and/or /ub.
data sheet m15406ej7v0ds 40 pd4632312-x figure 6-24. mode register setting timing chart /lb, /ub (input) /we (input) /cs (input) address (input) /oe (input) i/o (input) t rc t rc t wc t wc 1fffffh t wp t wr t wp t wr t dw t dh t dw t dh 1fffffh 1fffffh 1fffffh xxxxh xxxxh mode register setting figure 6-25. mode register setting flow chart start end address= 1fffffh read with toggled the /cs, /oe address = 1fffffh write data = 00h? no mode register setting exit fail address = 1fffffh write data = xxh? no note note xxh = 00h, 01h, 02h, 03h, 04h, 05h, 06h, 07h no no no no address= 1fffffh read with toggled the /cs, /oe
data sheet m15406ej7v0ds 41 pd4632312-x figure 6-26. standby mode timing chart /cs (input) t cm t mc mode (input) standby mode 1 standby mode 2 (data hold 16m bits / 8m bits / 4m bits) figure 6-27. standby mode 2 (data invalid) entry / recovery timing chart address (input) /cs (input) mode (input) t cm t rc t cp standby mode 2 (data invalid) read operation 3 times normal operation wait time 200 s
data sheet m15406ej7v0ds 42 pd4632312-x 7. package drawing 77-pin tape fbga (12x7) s x e ab m s wb w sa s y s y1 item millimeters d 12.0 0.1 7.0 0.1 e 0.2 b 0.45 0.05 x 0.08 y 0.1 y1 0.1 zd 0.7 ze 0.8 w a 1.1 0.1 a1 0.26 0.05 a2 0.84 p77f9-80-bt3 b ? index mark a 0.8 e a1 a2 s a b zd ze pnmlkjhgfedcba 8 7 6 5 4 3 2 1 d e
data sheet m15406ej7v0ds 43 pd4632312-x 8. recommended soldering conditions please consult with our sales offices for soldering conditions of the pd4632312-x. types of surface mount device pd4632312f9-bxxx-bt3: 77-pin tape fbga (12 x 7) pd4632312f9-cxxx-bt3: 77-pin tape fbga (12 x 7) pd4632312f9-bexxx-bt3: 77-pin tape fbga (12 x 7) pd4632312f9-cexxx-bt3: 77-pin tape fbga (12 x 7)
data sheet m15406ej7v0ds 44 pd4632312-x 9. revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 6th edition/ throughout modification preliminary data sheet data sheet jan.2002 p.9 p.9 modification 2.4 addresses for which 5cross beam 6cross beam partial refresh is supported 7th edition/ p.4 p.4 addition block diagram note mar. 2002 p.5 p.5 modification truth table standby mode 2 : /cs = h notes 1 revision
data sheet m15406ej7v0ds 45 pd4632312-x [ memo ]
data sheet m15406ej7v0ds 46 pd4632312-x [ memo ]
data sheet m15406ej7v0ds 47 pd4632312-x notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd4632312-x m8e 00. 4 the information in this document is current as of march, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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